This invention relates to a data processor in which vector element data denoted in the list vector format are fetched from and stored into a main storage at high speed in order to execute a vector operation.
An example of the method of denoting the list vector format is indicated in FIG. 1(a). This figure signifies that, from within a group of vector element data (hereinafter, simply written "data") D(1-10) consisting of 10 elements, the data of: EQU D(A(1-5))={D(A(1)), D(A(2)), D(A(3)), D(A(4)), D(A(5))}
is selected in accordance with the content of an indirect address vector (A(1-5) consisting of 5 elements representing an indirect address. That is, as illustrated in FIG. 1(b), within the data D(1-10) stored in a main storage, vector elements D(2), D(3), D(5), D(7) and D(10) which are respectively assigned by the indirect address vector elements A(1-5) are selected. Each element of the indirect address vector A(1-5) indicates the distance from the start address of the data D(1-10), i.e., D(1) to the elements D(i) to be assigned (address difference of these elements). Hereinbelow, this distance shall be called the "indirect address".
It is now supposed that the elements of data D(1-m) and the elements of an indirect address vector A(1-n) are respectively stored in the main storage regularly at equal distances and that m.gtoreq.n holds. The distance between the adjacent elements of the indirect address vector shall be termed an "increment value". The steps to be performed in the case of fetching data D(A(1-n)) from the main storage under such conditions will be described with reference to FIGS. 2(a) and 2(b).
FIG. 2(a) shows the outline of an address adding circuit, which may be used in a vector processor. FIG. 2(b) shows a time chart of a data fetch operation in the case of n=5. Before fetching the data, an increment value is set in an increment register 4, and the address of the first element D(1) of fetch data D(1-m) is set in an address register 3, and the address of a main storage (not shown) in which the first address A(1) of an indirect address vector A(1-5) is stored is set in an address register 2 through the selector 10.
First, the value of the address register 2 and the value zero are applied to an address adder 11 through a selector 14 and a selector 15, respectively. The added result, which comprises an address of the indirect address A(1) in the main storage, is stored into an address register 12, and it is thereafter transmitted to the main storage, as part of a read request. Simultaneously, the value stored in the address register 12 is set in the address register 2 through the selector 10.
Subsequently, the indirect address A(1) is read out from the main storage and is set in an address register 51. The values stored in the address register 3 and in the address register 51 are applied to the address adder 11 through the selector 14 and the selector 15, respectively. The added result, i.e., the address of an element D(A(1)), is transmitted to the main storage through the address register 12, as part of a read request. Next, the element D(A(1)) is read out from the main storage, to end the fetch processing of the first element D(A(1)).
Subsequently, in order to fetch an element D(A(2)), the values of the address register 2 and the increment register 4 are applied to the adder 11 through the selectors 14 and 15, respectively. The results of the addition, which comprises the address of the indirect address A(2) in the main storage, is stored in the address register 12. Thereafter, the main storage is accessed by the use of the address of the indirect address A(2), and the indirect address A(2) is set in the register 51. The indirect address A(2) and the content of the register 3 are applied to the adder 11 through the selectors 15 and 14, respectively, and the added result is used to read out the element D(A(2)) from the main storage.
Thereafter, the processings of the third and fifth elements are similarly executed to read out data D(A(3-5)). In this manner, the various processings of the read request of the indirect address A(i), the readout of A(i), the address calculation of the element D(A(i)) as well as the read request of D(A(i)), and the readout of D(A(i)) have ended, whereupon the processing of the next (i+1)-th element is executed.
However, it will be noted from the above description that the various processings for a plurality of elements cannot be overlapped. This leads to the problem that the speed of the vector data read-out operation becomes slow.
While the above description has been made of the case of reading out the data in the list vector indication, a similar problem is involved in case of writing data. As an example of the writing operation, there is considered a case where, in FIGS. 1(a) and 1(b), the data D(A(1-5)) is deemed an output result in a certain operation, and this value is written into a position for the data D(1-10) allotted in the main storage, in accordance with the value of the indirect address vector A(1-5). In this case, the indirect address vector A(1-5) may be either set in the main storage of, with the output result of a certain operation, stored in a vector register (registers for storing vector element data). In either case, there is the problem that the time of processing vector data is long.